&EPA
                         United States
                         Environmental Protection
                         Agency
                                     National Risk Management
                                     Research Laboratory
                                     Cincinnati, OH 45268
                          Research and Development
                                     EPA/600/S-95/020  September 1995
ENVIRONMENTAL
RESEARCH   BRIEF
                          Pollution Prevention Assessment for a
                                 Printed Circuit Board Plant

                               Harry W. Edwards*, Michael F. Kostrzewa*,
                                        and Gwen P. Looby"
Abstract
The U.S. Environmental Protection Agency (EPA) has funded
a pilot project to assist small and medium-size manufacturers
who want to minimize their generation of waste but who lack
the expertise to do so. In an effort to assist these manufactur-
ers Waste Minimization Assessment Centers  (WMACs) were
established at selected universities and procedures were
adapted from the  EPA Waste Minimization  Opportunity As-
sessment Manual (EPA/625/7-88/003, July 1988).  That docu-
ment has been superseded by the Facility Pollution Prevention
Guide (EPA/600/R-92/088,  May 1992). The  WMAC team  at
Colorado State University performed an assessment at a plant
that manufactures  printed circuit boards.  Templates for the
circuit design  are  generated  from  customer-supplied  circuit
information. Copper/epoxy laminates and copper foil are cut
into blank boards and layers.  Circuit patterns are generated
through  a series of photolithographic and plating processes.
The team's report,  detailing findings and recommendations,
indicated that  the onsite ion-exchange treatment of  metal-
containing rinse water generates regenerant solutions that could
be further treated by electrowinning to recover metals and  to
achieve  significant cost savings.

This Research Brief was developed  by the principal investiga-
tors and EPA's National Risk Management Research Labora-
tory, Cincinnati, OH, to  announce key findings of an ongoing
research project that is fully documented in a separate report
of the same title available from University City Science Center.
* Colorado State University, Department of Mechanical Engineering
* University City Science Center, Philadelphia, PA
                         Introduction
                         The amount of waste generated by industrial plants has be-
                         come an increasingly costly problem for manufacturers and an
                         additional stress  on the environment.  One  solution to the
                         problem of waste generation  is to reduce or eliminate the
                         waste at its source.

                         University City Science Center (Philadelphia, PA) has begun a
                         pilot project to assist small and medium-size manufacturers
                         who want to minimize their generation of waste but who lack
                         the in-house expertise to do so. Under agreement with EPA's
                         National Risk Management Research Laboratory, the Science
                         Center has established three WMACs. This assessment was
                         done by engineering faculty and students at  Colorado State
                         University's  (Fort Collins) WMAC.  The assessment teams
                         have considerable direct experience with process operations in
                         manufacturing plants and also have the knowledge and skills
                         needed to minimize waste generation.

                         The pollution prevention opportunity assessments are done for
                         small and medium-size manufacturers at no out-of-pocket cost
                         to the client.  To  qualify for the assessment, each client must
                         fall within Standard Industrial Classification Code 20-39, have
                         gross annual sales not exceeding $75 million, employ no more
                         than 500 persons, and lack in-house expertise  in  pollution
                         prevention.

                         The potential benefits of the pilot project include minimization
                         of the amount of waste  generated by  manufacturers, and
                         reduction of waste treatment and disposal costs for participat-
                         ing plants. In addition, the project provides valuable experi-
                         ence for graduate and undergraduate students who participate
                         in the program, and a cleaner environment without more regu-
                         lations and higher costs for manufacturers.

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Methodology of Assessments
The pollution prevention opportunity assessments require sev-
eral site visits to each client served.  In general, the WMACs
follow the procedures outlined in the EPA Waste Minimization
Opportunity Assessment Manual  (EPA/625/7-88/003, July 1988).
The WMAC staff locate the sources of waste in the plant and
identify the  current disposal or treatment  methods and their
associated costs.   They then identify and analyze a variety of
ways to reduce or eliminate the waste.   Specific measures to
achieve that goal are recommended and the essential support-
ing technological and economic information is developed. Fi-
nally,  a confidential report that details  the WMAC's  findings
and recommendations (including cost savings, implementation
costs, and payback times) is prepared for each  client.


Plant Background
This  plant  manufactures printed circuit boards.   It operates
approximately 4700 hr/yr to produce about  100,000 ft2 of prod-
uct annually.


Manufacturing Process
The  plant,  which  functions  as  a job-  and small-production-
shop, produces single-sided, double-sided, and multi-layer cir-
cuit boards.

Circuit information is received from customers  as blueprints,
films, computer diskettes, or computer-generated artwork. Cir-
cuit information that is  received as artwork is digitized and
computer-stored.  The template for the circuit design, known as
the working  film, is laser-generated from the customer's circuit
information.  Programs that provide drilling instructions for the
computer-controlled drilling machines are generated digitally.

The  raw materials for  printed circuit boards include copper/
epoxy laminates and copper foil.   Laminates and foil are cut
into blank boards and layers using  hydraulic shears.  Compo-
nent holes are then generated in the blank boards using high-
speed, numerically-controlled drilling machines.   The  drilled
boards are mechanically scrubbed in preparation for plating.

Circuit patterns are created  on  the individual layers of multi-
layer boards with dry-film, positive-image photoresist. The first
step  in transferring the electrical circuit design to the individual
layers is  laminating a UV-sensitive dry-film photoresist  to the
layers.  An image of the design  is generated by placing  a
template  of the circuit over the film and exposing the film to UV
light.  Exposed film is polymerized and protects the underlying
copper circuitry and unexposed photoresist is removed with an
aqueous  developing solution and rinse.  Unwanted copper is
then  removed with an ammonia/hydrogen peroxide  etchant.
The remaining protective film is removed with an alkaline resist
stripper leaving the desired copper circuitry. Fiberglass weave
sheets impregnated with resin are placed between each layer,
and the  array  is  heated  and bonded  in  a hydraulic  press.
Component holes are then drilled in the  multi-layer panels, and
the holes are cleaned  with a  sulfuric acid-based de-smear
solution.  Further processing of multi-layer boards is identical
to that of single and double-sided boards.
series of photolithographic  and plating processes.   First, the
surfaces are  copper-plated  in  an  electroless plating process.
This process  deposits copper on all exposed surfaces, includ-
ing the surfaces of drilled holes. Photoresist is then laminated
to the  board surfaces.   Additional copper is electrolytically
plated  on the surface circuit  patterns.   After  cleaning, the
pattern  is electrolytically plated with tin/lead solder to protect
the copper circuity during  subsequent steps to remove the
resist film and unwanted copper. The tin/lead layer is removed
following resist stripping and copper etching. A solder mask is
silk-screened and thermally cured to the board surfaces prior
to dipping the boards in molten tin/lead  solder.   The solder
layer provides the customer with a surface for mounting electri-
cal components.  Additional  processing involves conditioning of
the soldered  surfaces, cleaning,  rinsing, and  inspecting the
finished circuit boards.  Final processing includes silk-screen
application  of a legend, routing, rinsing, electrical testing,  in-
spections, packaging, and shipping.

An abbreviated process  flow  diagram for  the  production of
printed circuit boards is shown  in Figure 1.


Existing Waste Management Practices
This plant already has implemented the following techniques to
manage and mint flowing rinses.


Pollution Prevention Opportunities
The type of waste currently  generated by the plant, the source
of the waste, the  waste management method, the quantity of
the waste,  and the waste management cost  for each waste
stream identified are given in Table 1.

Table 2 shows the opportunities for pollution prevention that
the WMAC team recommended for the plant. The opportunity,
the type of waste, the possible waste reduction and associated
savings,  and the  implementation  cost along with the simple
payback time are given  in the  table.  The quantities of waste
currently generated by the plant and possible waste  reduction
depend  on the production level of the plant.  All values should
be considered in that context.

It should be noted that the economic savings of the opportuni-
ties,  in most cases, results from reduction in raw material and
costs associated  with waste treatment and disposal.   Other
savings not quantifiable by this study include a wide variety of
possible future costs related to changing emissions standards,
liability,  and employee health.  It also should be noted that the
savings given for  each opportunity that  pollution prevention
opportunity alone  and do not reflect  duplication of savings that
may result when the opportunities are implemented in a pack-
age.

This research brief summarizes a part of the work done under
Cooperative Agreement No. CR-819557 by the University City
Science Center under the sponsorship of the U. S. Environ-
mental Protection Agency. The EPA Project  Officer was Emma
Lou  George.
The  circuit patterns for  single and double-sided boards,  and
the outer layers  of the multi-layer boards are generated by a

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               Circuit Design
           Copper/Epoxy Laminates,
                  Copper Foil
?
Laser Generation
of Working Film



Dry Film Application,
Exposure, and
Development




T
Cutting and
Drilling

                          Copper Etch and
                          Resist Stripping
                            Baking and
                          Bonding of Layers
                         Electroless Copper
                              Plating
                         Dry Film Application
                          and Development
                              Cleaning
                         Electrolytic Copper
                              Plating
Electrolytic Tin/Lead
      Plating
  Resist Strip and
   Copper Etch
  Solder Stripping
   Solder Reflow
   Silkscreening
      Routing
                                                                                       Circuit Boards Packaged and
                                                                                          Shipped to Customers
Figurel. Abbreviated process flow diagram for circuit board production.

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United States
Environmental Protection Agency
National Risk Management Research Laboratory (G-72)
Cincinnati, OH 45268

Official Business
Penalty for Private Use
$300
     BULK RATE
POSTAGE & FEES PAID
        EPA
   PERMIT No. G-35
EPA/600/S-95/020

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